Design and Test of the PowerPCTM 603 Microprocessor

The PowerPC 603 1 microprocessor is a powerful lowcost implementation of the PowerPC ArchitectureTM specification. The structured design, logic verification and test data generation methodologies of the 603 are presented in this paper. The success of these methodologies has been demonstrated by meeting the 603’s aggressive time-to-market goals. 1.0 The PowerPC 603TM Microprocessor The 603 is the second member of the PowerPC microprocessor family[1]. The 603 is a powerful low-cost superscalar implementation of the PowerPC Architecture specification[2]. The 1.6 million transistor, 85 mm2 chip features on-chip 8Kbyte instruction and data caches coupled to a high performance 32/64-bit system bus. Power dissipation is under 3 watts at 80Mhz. Board and system test are supported using the JTAG IEEE P1149.1 port. A simplified block diagram of the 603 is shown in Fig 1. A maximum of two instructions per clock cycle are fetched from the instruction cache into the instruction buffers and branch unit. The branch unit executes any branch in the prefetch buffer and redirects the prefetch unit accordingly. The dispatcher decodes two instructions at a time from the instruction buffer and dispatches them if possible to available execution units: System unit, Integer unit, Floating point unit and Load/Store unit. The dual 8K-byte data and instruction caches have associated memory management units (MMUs) which implement the PowerPC Virtual Enviroment Architec1. In this document, the terms “PowerPC 603 Microprocessor” and “603” are used to denote the second implementation of the PowerPC microprocessor family. IBM, PowerPC, PowerPC 603, PowerPC Architecture and PowerPC 601 are trademarks of International Business Machines Corporation. Design and Test of the PowerPCTM 603 Microprocessor E. Kofi Vida-Torku*, Charles H. Malley**, Sung Park*, Rowland Reed* * International Business Machines Corp., ** Motorola Inc. Somerset Design Center 9737 Great Hills Trail Austin, Texas 78758 ture[2]. The processor bus interface unit (BIU) accepts bus requests from the instruction and data caches and places the requests on the 603 external bus. A common on-chip processor (COP) and JTAG controller are used to control test features of the chip. Some of the power reduction features are discussed in the next section followed by the 603 design methodology. Section three covers the functional, logic and physical verification process. Finally, the logic and array design for test methodology is presented. 1.1 Low Power features The goal of the 603 design was to optimize for performance, power consumption and cost. One hard limit was set by the portable computer systems, which required the typical processor power dissipation be no more than 3W. Therefore, many design choices were made to minimize power consumption[3]. The 603 implements a Phase Lock Loop (PLL) for synchronizing the internal clock to the system clock (bus clock). The PLL provides the internal clock frequency to be 1-4X integer multiples of the bus clock up to the Figure 1: 603 Block Diagram GPRs FPRs Instruction Decode Instr. Branch Buffer Unit External Bus Instruction MMU/ 8-Kbyte Instruction Cache JTAG/COP BIU Data MMU/ 8kB Data Cache System